The silicon used in most computer chips faces limitations in power handling, affecting the speed and energy efficiency of wireless systems. A potential solution lies in using gallium nitride transistors, which can meet the speed and energy demands of applications like 6G and satellite communications. However, these transistors generate significant heat, and when densely packed on a silicon chip, they create hot spots that reduce reliability and performance.
A team from MIT and other institutions has addressed this issue by embedding gallium nitride transistors in an ultrathin diamond layer. This diamond layer acts as a heat spreader, balancing the temperature and enabling the transistors to reach optimal performance without compromising reliability. The team’s method was used to create a power amplifier for wireless communications, surpassing all similar amplifiers in existing literature.
The fabrication process, although precise and involving multiple material systems, can be scaled for commercial use. “No single material can do everything well in a wireless device, so these 3D heterogeneously integrated systems are here to stay,” says Pradyot Yadav, an EECS graduate student at MIT and lead author of the study. Yadav collaborated with Tomás Palacios, Ruonan Han, and others at Georgia Tech and Penn State University. Their findings were presented at the Radio Frequency Integrated Circuits Symposium.
To enhance electronics, researchers are exploring systems where different materials are stacked together, each contributing its unique properties. MIT researchers have previously combined gallium nitride with silicon and glass to improve chip performance. However, varying operating temperatures among materials in such systems can reduce device reliability. “If we can incorporate a material that manages the heat so the GaN and silicon are at the same temperature, then the reliability of the entire 3D chip will improve,” Yadav explains, noting diamond as the best material for this purpose.
The team utilized lab-grown, jewelry-grade diamond, which has the highest thermal conductivity known. Advances in diamond growth have lowered costs, making them viable for chip use. While previous methods involved growing diamond layers on GaN transistors, this was difficult to scale and introduced unwanted capacitances. The MIT team developed a new approach, embedding tiny GaN transistors into a diamond interposer, managing heat without adding capacitances.
“By putting these GaN transistors into a diamond interposer, we are actually able to improve the performance of the device, as opposed to degrading it. We can get the best of both worlds,” Yadav says. The process starts with using a femtosecond laser to cut gallium nitride dielets, which are then placed in precisely drilled cavities in the diamond substrate. A thin die attach film is used to secure the dielets, ensuring efficient heat flow.
Additional dielectric and metal layers are added to create a functional circuit. This technique was used to construct a power amplifier, a vital component of wireless systems. The amplifier achieved superior output power, efficiency, and gain compared to previous models, including the team’s prior designs. “The power amplifier is the beating heart of a wireless device front end. Its performance will dictate the entire performance of your communication system,” Yadav states.
The results indicate the method’s suitability for high-power radars, space communications, and industrial drones, as well as improving energy efficiency in data center power conversions. Yadav hopes this work inspires further advancements in complex heterogeneously integrated systems, paving the way for future electronics. “GaN and 3D heterogeneous systems are going to be at the forefront of so many future applications. It is rewarding to know that we contributed a little bit to that space,” he says.
This research received funding from the Department of War, the Air Force Office of Scientific Research, the MIT Institute for Soldier Nanotechnologies, and Qualcomm Innovation Fellowships. Device fabrication and microscopy were carried out at MIT.nano and the Georgia Tech Institute for Matter and Systems.
Original Source: news.mit.edu
